William Computer Engineering University of Toronto

Major: BASc in Computer Engineering

Minor: Artificial Intelligence & Engineering Business

Dean's Honour List: All semesters

Relevant Courses:

• APS105: Computer Fundamentals (C)
• APS106: Fundamentals of Computer Programming (Python)
• ECE212: Circuit Analysis
• ECE241: Digital Systems (Verilog)
• ECE244: Programming Fundamentals (C++)
• MAT290: Advanced Engineering Mathematics
• MAT291: Calculus III
• ECE216: Signals and Systems
• ECE221: Electric and Magnetic Fields
• ECE231: Introductory Electronics
• ECE243: Computer Organization (Assembly NIOS II)
• ECE297: Software Design and Communication
• ECE302: Probability and Applications
• ECE344: Operating Systems
• ECE345: Algorithms and Data Structures
• ECE421: Introduction to Machine Learning
• APS360: Applied Fundamentals of Deep Learning
• CSC384: Introduction to Artificial Intelligence
• ECE311: Introduction to Control Systems
• ECE361: Computer Networks
• CSC343: Introduction to Databases

About the institution: York University is one of Canada's largest research universities, located in Toronto, Ontario. Its Lassonde School of Engineering conducts research across computer engineering, artificial intelligence, and emerging hardware, including in-memory and analog computing for energy-efficient machine learning.

Location: Toronto, Ontario, Canada

Department: Lassonde School of Engineering

Role Description:
As a Machine Learning Researcher at York University, I work under Dr. Amirali Amirsoleimani on analog in-memory computing for large language model inference, focusing on making transformer models reliable on noisy, non-ideal hardware. I investigated how large language models can be deployed entirely on analog in-memory computing (CIM) hardware that degrades over time. Analog tiles introduce weight noise that grows with drift, thermal variation, and faults, and every weight matrix in a transformer reacts to that noise differently. My work built a five-phase research pipeline around GPT-2 and IBM's AIHWKit to measure that sensitivity and use it to decide where each weight shard should live on a heterogeneous, aging tile substrate. The results are currently being written up as a letter, "Sensitivity-Aware Placement Sustains All-Analog GPT-2 Inference on Aging In-Memory Tiles," with IEEE Computer Architecture Letters (CAL) as the intended venue.

Projects:

• Phase 0: Hardware-Aware Fine-Tuning of GPT-2
  Fine-tuned GPT-2 Small on WikiText-103 under a documented analog noise contract, injecting clipped Gaussian weight noise in the forward pass while keeping clean updates, so that a fully analog deployment remains functional.


• Phase 1: Projection Sensitivity Profiling
  Profiled all 49 weight projections of GPT-2 (attention, MLP, and LM head) one at a time on analog tiles to measure the change in negative log-likelihood caused by analog noise. Added a leave-one-out check to confirm the ranking stays stable when every projection is noisy at once.


• Phase 2: Tile-Fidelity Aging Simulator
  Built a NumPy simulator of a heterogeneous tile-and-tier CIM substrate that produces time-varying per-tile noise traces covering manufacturing heterogeneity, gradual drift, thermal variation, and localized faults.


• Phase 3: Sensitivity-Aware Sharding and Placement
  Designed a sharding scheme that splits each weight matrix into crossbar shards while preserving fused Q/K/V boundaries, then implemented a sensitivity-aware placement policy and compared it against random, sequential, and hardware-only baselines.


• Phase 4: All-Analog Quality Evaluation
  Evaluated every placement policy on the full WikiText-103 test set through AIHWKit using paired noise realizations across multiple hardware seeds, tracking perplexity as the tiles age. Also built a digital/analog hybrid comparator that keeps the most sensitive projections digital, to study whether sensitivity-aware placement holds language-model quality better than workload-blind baselines as the hardware degrades.


• Reproducible Research Infrastructure
  Wrote the end-to-end pipeline driver with checkpoint resumption, multi-seed aggregation, cross-phase contract validation, a pytest suite, and a Google Colab runbook, and published the code on GitHub.

About the company: Huawei Canada is a subsidiary of Huawei Technologies, a global leader in information and communications technology (ICT) solutions. Established in 2008, Huawei Canada is headquartered in Markham, Ontario, and focuses on driving innovation through research and development in advanced technologies such as 5G, artificial intelligence, cloud computing, and telecommunications. With a commitment to building a connected and intelligent future, Huawei Canada partners with leading universities and institutions to foster technological advancements. The company plays a vital role in Huawei's global strategy, contributing to cutting-edge solutions and fostering Canada's technology ecosystem.

Location: Markham, Ontario, Canada

Department: Heterogeneous Compiler Lab

Role Description:
At Huawei’s Heterogeneous Compiler Lab, I worked on the Co-Design Team, contributing to the research and development of instruction prefetching optimizations for the BiSheng compiler, a production-grade LLVM-based compiler tailored for ARM-based mobile SoCs. My work focused on leveraging runtime profiling data to optimize the structure of the Control Flow Graph (CFG) and support compiler-assisted execution prediction. This was critical in reducing memory latency, improving instruction locality, and ultimately enhancing the runtime performance of mobile applications.

Projects:

• Instruction Prefetching with Control Flow Analysis
  Designed and implemented an optimization pipeline that used BRBE (Branch Record Buffer Extension) samples collected via perf to identify hot paths in the control flow graph. These hot paths were used to guide instruction prefetching, aiming to reduce stall cycles and improve front-end throughput.


• Control Flow Graph Refinement with Heuristics
  Improved the accuracy of the CFG by removing noise introduced by ordinary and inlined PLT (Procedure Linkage Table) entries. Developed a weighted propagation algorithm that used branch statistics (taken/fallthrough) to propagate execution weight more realistically across basic blocks. Result: Achieved a 89% increase in basic block coverage, significantly improving the effectiveness of downstream optimizations.


• Cross-Library Call Bypass Mechanism
  Implemented logic to trace and eliminate unnecessary cross-library transitions via the PLT. This allowed the CFG to maintain a cleaner intra-library representation, enabling more accurate intra-library optimizations. Impact: Reduced irrelevant branch noise by over 70%, leading to better profiling fidelity and lower overhead in analysis.


• Execution-Based Function Reordering
  Used instruction-level execution frequency data to reorder functions in the binary, minimizing page faults and improving spatial locality. Result: Achieved a 57% reduction in page utilization, boosting memory efficiency for performance-critical paths.


• End-to-End Automation of ELF Generation Pipeline
  Developed a fully automated pipeline to generate annotated ELF files, starting from trace collection on mobile devices using hiperf, all the way to DBI (Dynamic Binary Instrumentation) and CFG parsing. This involved scripting complex dataflows and synchronizing logs, trace dumps, and symbols to integrate with existing compiler tools.

About the company: BTG Pactual is the leading investment bank in Latin America, renowned for its excellence in financial services and innovative solutions. Headquartered in São Paulo, Brazil, it specializes in investment banking, asset management, wealth management, and corporate lending. Recognized as the best investment bank in the region, BTG Pactual combines deep market expertise with cutting-edge technology to deliver exceptional value to its clients. With a strong presence across Latin America and a global reach, it continues to set the standard for financial performance and client-focused strategies.

Location: Sao Paulo, Sao Paulo, Brazil

Department: Small and medium-sized enterprises (SMEs)

Role Description: As a Software Engineer Intern at BTG Pactual within the Business Banking department, I worked on developing full-stack features to enhance cashout operations for small and medium-sized enterprises (SMEs). These operations included payments, bank slips, and taxes. Collaborating with a cross-functional team, I designed, implemented, and tested secure and scalable solutions to improve banking services for clients.

Projects:

• Payment Modification Feature: Developed a feature to allow businesses to modify scheduled payments, including changes to the debit party, credit party, amount, and payment date.
  • Designed and developed front-end components using React for modifying scheduled payments. The feature included a form page for entering payment details, a review page for confirmation, and a feedback page for post-submission actions. Focused on building intuitive and reusable components that seamlessly integrated with the back-end API to enable real-time updates.
  • Developed a secure back-end API using Node.js and NestJS to handle payment modifications, including changes to the debit party, credit party, amount, and payment date. Conducted unit testing with Jest to ensure reliability and accuracy of the API.


• Fraud Reporting Interface: A user-facing interface that enables clients to report fraudulent transactions by selecting the fraud type, providing detailed descriptions, and submitting reports to the fraud analysis team.
  • Created a user-friendly front-end interface that allowed clients to report fraud. The design included options to select the fraud type, provide detailed descriptions, and submit reports to the fraud analysis team.
  • Ensured a seamless user experience by focusing on accessibility and integration with the internal fraud-handling workflow.


• PagFor Infrastructure Automation: An automated accounts payable solution that simplifies and streamlines supplier payments by securely transmitting payment data between businesses and the bank.
  • Developed the back-end infrastructure for "PagFor," a solution to automate accounts payable for businesses by enabling seamless payment processing with suppliers.
  • Utilized Terraform to configure AWS services, including SQS and SNS, to handle event-driven workflows for PagFor. Ensured the system's scalability and reliability for handling high-volume transactions.

About the company: Honda of Canada Manufacturing (HCM) is Honda's Canadian automotive manufacturing facility located in Alliston, Ontario. Established in 1986, HCM is a cornerstone of Honda's global operations, producing high-quality vehicles for both domestic and international markets. The facility includes three manufacturing plants, specializing in vehicle assembly, engine manufacturing, and plastic injection molding. Known for its commitment to innovation, sustainability, and quality, HCM produces popular models like the Honda Civic and Honda CR-V. With a focus on advanced manufacturing technologies and a skilled workforce, HCM is a key player in the Canadian automotive industry.

Location: Alliston, Ontario, Canada

Department: Engine Plant - Die Casting

Role Description: As a Production Associate at Honda of Canada Manufacturing in the Engine Plant's Die Casting Department, I played a crucial role in ensuring the production of high-quality engine blocks and heads. My contributions spanned key areas of the manufacturing process, including die casting, final inspection, quality control, and sandmould preparation. I collaborated with the Machining and Assembly Department to uphold the highest standards of quality assurance, working extensively with machinery and both semi-automated and automated robots.

Projects:

• Die Casting:
  • Operated and monitored die-casting machinery to produce engine blocks and heads in accordance with strict specifications and quality standards.
  • During early shifts, I initialized the entire die-casting system, meticulously checking each point of the system to ensure optimal functionality.
  • Inspected every produced engine block for defects and reloaded engine cylinders as required to maintain uninterrupted production.
  • In cases of system malfunctions or crashes, I stopped the robots, diagnosed the issues, performed necessary repairs, and reinitialized the system to resume operations.
  • Ensured production targets were consistently met by maintaining efficiency and addressing any obstacles promptly.


• Quality Control:
  • Conducted detailed final inspections of cast engine blocks and heads, carefully identifying any defects or irregularities.
  • Ensured that only flawless components advanced to subsequent machining and assembly stages, maintaining Honda's commitment to top-quality products.


• Sandmould Preparation:
  • Prepared and maintained sand moulds used in the casting process, guaranteeing precision in dimensions and specifications.
  • Inspected the moulds for any defects, cleaned the machinery, and prepared it at the beginning of each shift to ensure smooth operations.
  • Ensured production targets were consistently met by maintaining efficiency and addressing any obstacles promptly.


• Machining and Assembly:
  • Partnered closely with the Machining and Assembly Department to confirm that all cast components adhered to quality requirements for further processing.
  • This collaboration was essential for maintaining production flow and ensuring seamless integration between departments.


• Machinery Operation:
  • Operated a variety of machinery, including semi-automated and automated robots, to support manufacturing and quality control processes.
  • Ensured the machinery operated efficiently and took corrective actions when issues arose to minimize downtime and maintain production goals.

About the company: The University of Toronto Robotics Association (UTRA) Autonomous Racing Team (ART) is a cutting-edge student team focused on developing autonomous vehicles capable of navigating challenging circuits and obstacles. Combining expertise in robotics, computer vision, machine learning, and control systems, the team participates in competitions that push the boundaries of autonomous navigation technology. Members collaborate on innovative solutions for real-world challenges, such as lane detection, obstacle avoidance, and real-time decision-making, contributing to advancements in autonomous systems while honing their technical and teamwork skills.

Department: Autonomous Racing Team (ART)

Role Description: As a Computer Vision member of the University of Toronto Robotics Association (UTRA), I contributed to the development and optimization of algorithms to enhance the robot's ability to navigate circuits with obstacles. The competition's objective was to ensure the robot avoided obstacles, remained within lanes, and completed the circuit in the shortest time possible. My role involved designing and implementing computer vision and machine learning techniques to improve the robot's perception and decision-making capabilities. Collaborating with a multidisciplinary team, I focused on algorithm development, data processing, model training, and system integration, ensuring the robot performed reliably in dynamic environments.

Projects:

• Lane Marking and Pothole Detection:
  • We developed both classical and deep learning algorithms for detecting lane markings and potholes. The classical method utilized Canny edge detection and grayscale transformation, achieving near-perfect accuracy (99% IOU) with a fast inference time of 25ms. We only run detection up to 70% of the frame height to reduce noise. Additionally, we process 8 frames at once, as they are very similar. The deep learning model, trained using advanced techniques, reached 91.6% accuracy for lane detection and 96% for pothole detection, with further optimization via parameter pruning improving inference speed to 9ms. The algorithm was tested using videos from previous years, achieving near 100% accuracy for the classical method and promising results during physical testing.


• Physical Obstacle Detection:
  • For obstacle detection, we employed the Slamtec RPLIDAR A1M8 for its high accuracy and speed, which proved more cost-effective compared to 3D LiDAR systems. We directly added detected lidar points to the map without filtering, simplifying the process. Ramp detection was excluded to prevent falsely identifying ramps as obstacles, thus reducing computational complexity. The system was capable of consistently detecting obstacles, with mapping accuracy confirmed in simulation, where detected obstacles were accurately placed within 1s.


• Ramp Navigation Mode:
  • We developed a robust ramp navigation mode to safely guide the rover across sloped surfaces. Using dual LiDAR sensors, the system detects proximity to ramps and interrupts the regular path planning. It then plans a safe path with waypoints spaced 0.5 meters apart, ensuring the rover remains within a 10° deviation while traversing the ramp. This method successfully navigated ramps 85% of the time, though optimization to reduce time cost is still in progress. This strategy was designed to address challenges such as risk of veering off and overshooting during ramp entry.


• Performance Evaluation and Optimization:
  • Conducted rigorous testing of vision algorithms in simulation and real-world scenarios to identify bottlenecks and optimize performance.
  • Tuned hyperparameters and evaluated algorithm efficiency to meet real-time processing requirements.


• System Integration:
  • Collaborated with team members responsible for control and navigation systems to integrate vision algorithms into the robot's overall architecture.
  • Ensured seamless communication between the vision module and other subsystems, enabling real-time decision-making and navigation.


• Team Collaboration and Documentation:
  • Worked closely with multidisciplinary team members to align vision capabilities with competition requirements.
  • Documented processes, algorithms, and results to facilitate knowledge sharing and future development.

Project Description: With over 55 million people affected globally, Alzheimer’s disease is the most common cause of dementia and remains notoriously difficult to diagnose in early stages. Motivated by this challenge, I worked with a team of four to design a deep learning-based diagnostic tool that leverages MRI brain scans to automatically classify the stage of Alzheimer’s progression. By enabling earlier and more accurate diagnosis, such models could support physicians in timely treatment decisions and reduce dependency on subjective clinical evaluation, especially in resource-constrained settings.

• Model Development: Designed and implemented a deep transfer learning pipeline using ResNet152, replacing its classifier head with a custom fully connected architecture tailored to four-stage Alzheimer’s classification (Non-Demented, Very Mild, Mild, Moderate).


• Performance Tuning: Fine-tuned layers 2–4 of ResNet152 and applied data augmentation (flip, rotation, contrast adjustment) to reduce overfitting, achieving 96.5% recall and 96.48% F1-score, minimizing false negatives crucial in medical diagnosis.


• Baseline Comparison: Benchmarked against a Random Forest classifier, improving accuracy from 74.25% to 96.5% (+22.25%) and recall by 30%, demonstrating the advantage of deep CNNs over classical ML.


• Optimization: Reduced training loss by 47.7% and validation error by 60.4% through hyperparameter tuning (learning rate: 5.2e-5, batch size: 16, epochs: 50)


• Data Pipeline Engineering: Preprocessed and one-hot encoded over 4,800+ MRI images, implemented robust data splitting (70/15/15) for training, validation, and testing; used PyTorch, NumPy, and Matplotlib for training and visualization.

Model predictions on sample MRI scans

Testing on Completely Unseen Data from External Sources:

Project Description: SWIFT Map is a Geographic Information System (GIS) application designed to provide interactive and efficient map rendering and routing capabilities for various cities. The system integrates geographic data from the OpenStreetMap (OSM) database, ensuring up-to-date and accurate information about city layouts, public routes, and intersections.

• Map Rendering: Implemented a map rendering feature that displays city layouts, streets, and landmarks using OpenStreetMap data. The system supports zooming, panning, and night mode.


• Shortest Path Finder: Allows users to determine the shortest path between two intersection points using A* algorithm. Users can input intersections manually by typing or select them interactively by clicking on the map, with the system automatically identifying the nearest intersection.


• Multiple Transportation Modes: Displays various transportation routes, including subways, buses, trams, trains, and bicycle paths, offering users a comprehensive view of public and alternative transport options.


• Wheelchair Accessibility: Implemented a feature that highlights transportation routes and stations that are wheelchair accessible, providing vital information for individuals with mobility challenges.


• Key Landmarks and Points of Interest: Displays important points such as hospitals, parks, schools, and other key landmarks, helping users locate essential facilities and recreational spaces within the city.

Path finding:

Public Transport Routes:

Wheelchair Accessibility:

Project Description: The Doodle Jump project is a classic arcade-style game developed as the final project for ECE243. Designed for play on an FPGA board with a PS/2 keyboard, the game challenges players to ascend an endless world by jumping between platforms, avoiding monsters, and achieving the highest possible score. The game mechanics and visuals are implemented with careful attention to randomness, user interaction, and real-time gameplay feedback.

• Interactive Gameplay: Players control a character using the arrow keys to move left and right, while the spacebar is used to start the game or reset after losing. The game features wrap-around mechanics, allowing the character to reappear on the opposite side of the screen when moving off the edge.


• Dynamic Platforms: Platform placement is randomized but carefully constrained to ensure progress is always possible. The game includes three types of platforms:
  • Green Platforms: Static, standard platforms that provide a stable jumping point.
  • Grey Platforms: Temporary platforms that disappear after the player jumps on them, adding an element of strategy.
  • Blue Platforms: Moving platforms that oscillate side to side, requiring timing and precision.


• Monsters and Hazards: Two types of monsters appear as obstacles, spawning randomly every 250 pixels ascended with a 1/4 probability. Monsters are strategically placed to provide a challenge while ensuring they remain visible on-screen.


• Scoring System: The player’s score increases as they ascend and is displayed in real time on the FPGA's HEX display. Falling off the visible world or colliding with a monster ends the game, resetting the score upon restarting.


• Real-Time Graphics and Logic: The game utilizes an FPGA-based system for real-time rendering and input processing, providing a seamless and responsive gaming experience.